The present invention relates to a semiconductor memory device, and more particularly, to technology that improves timing of a pipe-in signal, which is a signal conveying data to a pipe latch to allow data to be stably conveyed to the pipe latch.
A semiconductor memory device can receive commands successively from the outside but does not immediately perform the successively received commands. In case of a read operation, a read CAS signal (a kind of an internal read command) should be enabled to perform the read operation. A double data rate 2 (DDR2) semiconductor memory device internally secures a time for performing successive commands by delaying an enable point of the read CAS signal. A delay time until a read CAS signal controlling an internal operation is enabled by a read command is called an additive latency (AL). Also, a time taken until effective data is output from the CAS signal enabled by the additive latency is CAS latency (CL). That is, the read latency taken until a read command is applied and internal data is output is equal to the sum of AL and CL.
As described above, the semiconductor memory device stores data output from a memory array block by a read command in a latch, and outputs the data at a point corresponding to set CAS latency. This is for preventing collision with data successively output next in the case where data is output from the memory array block earlier than the set CAS latency.
Meanwhile, data of a plurality of bits can be output by applying a read command one time. The number of bits output at a time can be determined by setting a burst length of a mode register. Also, the sequence of output data can be determined by setting a burst type of the mode register. The data output sequence is divided into an interleave mode and a sequential mode, and each mode has a different data output sequence.
Specifically, the DDR2 uses a 4-bit prepatch outputting a 4-bit memory cell data per data pin DQ during a read operation.
FIG. 1 is a circuit diagram illustrating a data path of a conventional semiconductor memory device. The data path from a memory array block to an output pad is described.
During a read operation, data is applied from a memory cell 1 inside a memory array block to a bit line (BL, /BL) by a fine voltage. This data is detected by a bit line sense amplifier (BLSA) 2 and amplified to a full voltage level. The data of the bit line sense amplifier 2 is applied to a data bus LIO (LIOB) by a column select signal Y1 enabled by a column address, and this data is amplified again by a main amplifier (or IOSA) 3.
The data of the main amplifier 3 is stored in a pipe latch 4 through a global input/output line GIO, and output to an output driver 5 at a point corresponding to CAS latency. The output driver 5 outputs the data to the outside through a data pad DQ. A path from the main amplifier 3 to the output driver 5 is called a read path.
Also, when data is applied from the outside through the data pad 6 during a write operation, the data passes through a data input buffer 7 and is applied in a device. The output data of the data input buffer 7 is stored in a data input register 8, and transferred to a write driver 9 through a global input/output line GIO. The write driver 9 amplifies the data to transfer the data to a data bus. The data of the data bus is applied to the bit line BL (/BL) of the bit line sense amplifier 2 by a column select signal Y1 enabled by a column address. Therefore, the data applied to the bit line BL (/BL) is stored in the memory cell 1. A path from the data input buffer 7 to the write driver 9 is called a write path.
Hereinafter, the operation of a pipe latch is described in more detail.
FIG. 2 is a block diagram illustrating a global input/output line pipe latch and an output driver inside a conventional semiconductor memory device.
Global input/output lines GI00, GI01, GI02, and GI03 input data D0-D15 output by application of successive read commands to pipe latches 210, 220, 230, and 240 in parallel. D0, D1, D2, and D3, which are data initially arrive through the global input/output lines GI00, GI01, GI02, and GI03 are strobed by a pipe latch input signal PINB<0>, and input and stored in the pipe latch 210. D4, D5, D6, and D7, which are the next data are strobed by a pipe latch input signal PINB<1>, and input and stored in the pipe latch 220. Likewise, D8, D9, D10, and D11 are input and stored in the pipe latch 230 by a pipe latch input signal PINB<2>, and D12, D13, D14, and D15 are input and stored in the pipe latch 240 by a pipe latch input signal PINB<3>.
Data input to the same pipe latches 210, 220, 230, and 240 are data read by the same read command. When D0, D1, D2, and D3 are read by an initial read command, D4, D5, D6, and D7 are read by the next read command.
That is, whenever a read command is applied, pipe-in signals PINB<0:3> are sequentially enabled to input data of the global input/output lines GI00, GI01, GI02, and GI03 to corresponding pipe latches 210, 220, 230, and 240.
Data stored in the pipe latches 210, 220, 230, and 240 are strobed by RPOUTB<0:3> (strobing data of an RDO line) and FPOUTB<0:3> (strobing data of an FDO line), which are signals determining a timing that outputs data from each of the pipe latches 210, 220, 230, and 240, and output to an output driver 250. The output driver 250 outputs these data D0-D15 to the outside of a chip in series through a data pin.
How the data D0, D1, D2, and D3 transferred from the FDO line and the RDO line, which are output lines of the pipe latch 210, are converted and output in series has been briefly illustrated below the output driver 250 in the drawing (D4-D15 are converted in series likewise). The flow of the data D0-D15 can be understood with reference to this illustration.
The pipe latches 210, 220, 230, and 240 store the data D0-D15 to be output, and output the data to the outside of the chip at an appropriate timing, thereby preventing collision between the data D1-D15.
FIG. 3 is a circuit diagram illustrating a unit of the pipe latch 210 that receives data in order to describe the role of a pipe-in signal.
As illustrated in FIG. 3, the unit of the pipe latch 210 that receives data include inverters 311, 312, 313, and 314, enabled to receive data in response to a pipe-in signal PINB<0>, and latches 321, 322, 323, and 324.
While a pipe latch input signal PINB<0> is enabled to ‘low’, the inverters 311, 312, 313, and 314 are enabled to receive data D0, D1, D2, and D3 of the global input/output lines GI00, GI01, GI02, and GI03. The received data D0, D1, D2, and D3 are stored in the latches 321, 322, 323, and 324. The received data D0, D1, D2, and D3 pass through a circuit in the rear end of the pipe latches and are strobed by RPOUTB<0> and FPOUTB<0> signals, and output to the RDO and FDO lines. Consequently, the data D0, D1, D2, and D3 are output in series through the data pin DQ.
Though the sequence of outputting the data D0, D1, D2 and D3 can change depending on the sequential mode and the interleave mode, the sequence has nothing to do with the invention and description thereof is omitted.
For reference, the data input units of the other pipe latches 220-240 have the same construction as that of the pipe latch 210.
FIG. 4 is a block diagram illustrating a pipe-in signal generating part of a semiconductor memory device, and FIG. 5 is a timing diagram of the pipe-in signal generating part of FIG. 4.
Pipe-in signals PINB<0:3> are generated by a preliminary signal generator 410, a delay unit 420, a pulse width controller 430, and a pipe-in signal generator 440.
The preliminary signal generator 410 generates a preliminary pipe-in signal PINSTSUMB in response to main amplifier enable signals YMAE03 and YMAE47. The signal YMAE03 corresponds to a signal enabled when even one of main amplifiers IOSA of banks 0-3 is enabled. The signal YMAE47 corresponds to a signal enabled when even one of main amplifiers IOSA of banks 4-7 is enabled. The preliminary signal generator 410 enables a preliminary pipe-in signal PINSTSUMB when even one of signals YMAE03 and YMAE47 is enabled. That is, whenever a main amplifier is enabled regardless of the banks, the preliminary pipe-in signal PINSTSUMB is enabled in response thereto. Also, this means that the preliminary pipe-in signal PINSTSUMB is enabled whenever a read command is applied.
The delay unit 420 delays a preliminary pipe-in signal PINSTSUMB to output the same. Data amplified by the main amplifier 3 passes through a long global input/output line GIO and is transferred to the pipe latch 4. Therefore, the data passes through a considerable delay until the data arrive from the main amplifier 3 to the pipe latch 4, and a pipe-in signal PINB<0:3> that should arrive at a corresponding timing should be also delayed. The delay unit 420 provides this delay value. Though the delay unit 420 is illustrated as one block in the drawing, a simply long transmission line can have a sufficient delay value. Accordingly, the delay unit 420 can be a simply long transmission line.
The pulse width controller 430 controls the width, i.e., the pulse width of the enable section of a preliminary pipe-in signal PINSTSUMB whose delay value has been controlled by the delay unit 420, to output the same.
The pipe-in signal generator 440 sequentially enables pipe-in signals PINB<0:3> whenever a preliminary pipe-in signal PINPULSEB is enabled once. When a preliminary pipe-in signal PINPULSEB is enabled initially, PINB<0> is enabled, and after that, PINB<1>, PINB<2>, and PINB<3> are sequentially enabled. After PINB<3> is enabled, PINB<0> is enabled again. A reset signal RSTDOUTB is a signal initializing the operation of the pipe-in signal generator 440. When the reset signal RSTDOUTB is enabled, pipe-in signals are enabled again from PINB<0>. For example, when a reset signal RSTDOUTB is enabled after PINB<2> is enabled, and a preliminary pipe-in signal PINPULSEB is enabled, then pipe-in signals are enabled again from PINB<0>.
A process of generating pipe-in signals PINB<0:3> is described in sequence with reference to FIG. 5. When a read command is applied and main amplifiers of banks 0-3 are enabled (YMAE03 ‘high’) or main amplifiers of banks 4-7 are enabled (YMAE47 ‘high’), a preliminary pipe-in signal PINSTSUMB is enabled as ‘low’. Also, the preliminary pipe-in signal PINSTSUMB is delayed (PINDLYB) by the delay unit 420 to control a timing with data input, and the pulse width of an enable section is controlled (PINPULSEB) by the pulse width controller 430. Also, pipe-in signals PINB<0:3> are sequentially enabled as ‘low’ in response thereto.
FIGS. 6A and 6B are timing diagrams for explaining problems occurring when a pipe-in signal is generated using a conventional method.
Referring to FIG. 6A, a main amplifier enable signal YMAE (illustrated regardless of banks in the present drawing) is enabled and a main amplifier is enabled by application of a read command RD. Therefore, data D0 and D1 are transferred from local input/output lines LIO/LIOB to a global input/output line GIO. A pipe-in signal PINB<0> is enabled in response to a main amplifier enable signal YMAE enabled first. A pipe-in signal PINB<1> is enabled in response to a main amplifier enable signal YMAE enabled second. Also, the pipe-in signal PINB<0> inputs data D0 to a pipe latch, and the pipe-in signal PINB<1> inputs data D1 to a pipe latch.
At this point, since pipe-in signals PINB<0> and PINB<1> are enabled within the section of the data D0 and D1, the data D0 and D1 can be stably input to the latches.
FIG. 6B illustrates data transfer of a GIO gets slow and the timing of a pipe-in signal gets fast due to a condition change inside a chip.
Referring to FIG. 6B, a pipe-in signal PINB<0> can input data D0 to a pipe latch for only time T2, and a pipe-in signal PINB<1> can input data D1 to a pipe latch for only time T2.
The pipe-in signal PINB<1> is a signal inputting the data D1 to a pipe latch. Correct data D1 needs to be input until a pipe latch is closed (data stored before a pipe latch is closed by the disabled PINB<1> is D1). False data D0 is input when a pipe-in signal is enabled initially and then D1, which is correct data, is input later. However, the time T2 is so short that stably inputting data D1 to a pipe latch cannot be guaranteed.
In case of generating a pipe-in signal using a conventional method, data cannot be stably input to a pipe lath when a PVT condition, etc. inside a chip changes. Since a fact that data is not stably input to a pipe latch means that a memory device outputs false data consequently, a read operation failure is caused.